Today's computer systems are becoming increasingly sophisticated, permitting users to perform an ever greater variety of computing tasks at faster and faster rates. The size of the memory and the speed at which it can be accessed bear heavily upon the overall speed of the computer system.
Memory for a computer system is technically any form of electronic, magnetic or optical storage; however, it is generally divided up into different categories based in part upon speed and functionality. The two general categories of computer memory are main memory and mass storage. Main memory is generally comprised of fast, expensive volatile random access memory that is connected directly to the processor by a memory bus. One contributor to the speed in main memory is generally the ability to access a particular memory cell without physical movement of components.
Generally, the principle underlying the storage of data in magnetic media (main or mass storage) is the ability to change and/or reverse the relative orientation of the magnetization of a storage data bit (i.e. the logic state of a “0” or a “1”). The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and/or reverse the magnetization of the particle.
A prior art magnetic memory cell may be a tunneling magneto-resistance memory cell (TMR), a giant magneto-resistance memory cell (GMR), or a colossal magneto-resistance memory cell (CMR). These types of magnetic memory are commonly referred to as spin valve memory cells (SVM). FIGS. 1A and 1B provide a perspective view of a typical prior art magnetic memory cell having two conductors.
As shown in prior art FIGS. 1A and 1B, a magnetic spin valve memory cell 100 generally includes a data layer 101 (also called a storage layer or bit layer), a reference layer 103, and an intermediate layer 105 between the data layer 101 and the reference layer 103. The data layer 101, the reference layer 103, and the intermediate layer 105 can be made from one or more layers of material. Electrical current and magnetic fields may be provided to the SVM cell 100 by an electrically conductive row conductor 107 and an electrically conductive column conductor 109.
In a typical MRAM device, the SVM cells are arranged in a cross-point array. Parallel conductive columns (column 1, 2, 3 . . . ), also referred to as word lines, cross parallel conductive rows (row A, B, C . . . ), also referred to as bit lines. The traditional principles of column and row arrays dictate that any given row will only cross any given column once.
An SVM cell is placed at each intersecting cross-point between a row and column. By selecting a particular row (B) and a particular column (3), any one memory cell positioned at their intersection (B,3) can be isolated from any other memory cell in the array. Such individual indexing is not without complexities. A typical MRAM cross-point array may easily consist of at least 1,000 rows and 1,000 columns uniquely addressing 1,000,000 SVM cells.
The data layer 101 is usually a layer of magnetic material that stores a bit of data as an orientation of magnetization M2 that may be altered in response to the application of an external magnetic field or fields. More specifically, the orientation of magnetization M2 of the data layer 101 representing the logic state can be rotated (switched) from a first orientation, representing a logic state of “0”, to a second orientation, representing a logic state of “1”, and/or vice versa.
The reference layer 103 is usually a layer of magnetic material in which an orientation of magnetization M1 is “pinned”, as in fixed, in a predetermined direction. The direction is predetermined and established by microelectronic processing steps employed in the fabrication of the magnetic memory cell.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer 101 and the reference layer 103. For example, when an electrical potential bias is applied across the data layer 101 and the reference layer 103 in an SVM cell 100, electrons migrate between the data layer 101 and the reference layer 103 through the intermediate layer 105. The intermediate layer 105 is typically a thin dielectric layer commonly referred to as a tunnel barrier layer. The phenomena that cause the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling, or spin tunneling.
The logic state may be determined by measuring the resistance of the memory cell. For example, if the overall orientation of the magnetization in the data layer 101 is parallel to the pinned orientation of magnetization in the reference layer 103 the magnetic memory cell will be in a state of low resistance, R.
If the overall orientation of the magnetization in the data layer 101 is anti-parallel (opposite) to the pinned orientation of magnetization in the reference layer 103, the magnetic memory cell will be in a state of high resistance R+ΔR. The orientation of M2 and, therefore, the logic state of the SVM cell 100 may be read by sensing the resistance of the SVM cell 100.
With respect to coercivity, generally speaking, the smaller the magnetic particle, the higher its coercivity. A large coercivity is generally undesirable as it requires a greater magnetic field to facilitate switching, which in turn requires a greater power source and potentially larger conductors. Providing a large power source and large conductors is generally at odds with the attempts to reduce the necessary size of components, and therefore permit larger memory stores in smaller and smaller spaces.
In addition, the coercivity of a magnetic particle may also be affected by temperature. Generally, as temperature increases, coercivity decreases. With respect to MRAM and SVM cells, elevating the temperature of an SVM cell may indeed reduce the coercivity. In an MRAM array, switching the magnetic orientation of a specific cell without substantially disturbing the others can be facilitated by heating the selected cell, and thus lowering that particular SVM cell's coercivity. Such a heated SVM cell may then be switched by a field that is insufficient to affect unselected neighboring SVM cells.
However, environmental factors may significantly affect the SVM cell. Heat applied to an SVM cell in one setting to reduce it's coercivity may be ineffective in another, i.e., where the cell is extremely cold.
Likewise, where the ambient temperature is extremely warm, additional heat (and the switching field itself) may inadvertently affect more than the specifically intended SVM cell. The variable of ambient temperature and the effect on the operation of the MRAM can therefore degrade proper operation of the SVM cells.
In a typical MRAM array, a significant amount of overall space may be used simply to provide a physical buffer between the cells. Eliminating this buffering space, or reducing its ratio, could provide a greater volume of storage in the same physical space
Hence, there is a need for an ultra-high density thermally assisted memory array which overcomes one or more of the drawbacks identified above. The present invention satisfies this need.